Research on Circuit Level Protection Design of SRAM Single Event Latch-up Effect

被引：0

作者：

Wu H. ^{[1
,2
]}

Zhu X. ^{[1
]}

Han J. ^{[1
]}

Shangguan S. ^{[1
]}

Ma Y. ^{[1
]}

Li Y. ^{[1
]}

Zhao X. ^{[1
]}

Yang H. ^{[1
,2
]}

机构：

[1] National Space Science Center, Chinese Academy of Sciences, Beijing

[2] University of Chinese Academy of Sciences, Beijing

来源：

Yuanzineng Kexue Jishu/Atomic Energy Science and Technology | 2022年 / 56卷 / 04期

基金：

日本学术振兴会;

关键词：

Circuit level protection; Pulse laser; Single event latch-up; Static random access memory;

D O I：

10.7538/yzk.2021.youxian.0733

中图分类号：

学科分类号：

摘要：

SRAM with high density CMOS technology is extremely sensitive to single event latch-up, so it is necessary to adopt corresponding protection strategies in space applications. For COTS with reduced radiation resistance, circuit level protection becomes an important part to improve system reliability. A series of single event latch-up effect tests were carried out on CY62167DV30LL SRAM of CYPRESS Company by using laser single event effect test device. Through the linear fitting of the experimental results, the holding voltage of the SRAM is 1.5-1.6 V, and the holding current is 9.9-11.2 mA. According to the holding current, holding voltage, working current and working voltage, judge whether circuit level protection can be adopted. Two circuit level protection methods of power supply current limiting and divider resistor were proposed, and the value range of power supply current limiting and divider resistor were calculated quantitatively. In the previous literature, resistor is only used as a means of current limiting after latch-up trigger, which can not prevent the device from latch-up. It is found that the divider resistor can also achieve the purpose of preventing the latch-up under certain conditions. The two protection methods were verified by pulse laser test. © 2022, Editorial Board of Atomic Energy Science and Technology. All right reserved.

引用

页码：758 / 766

页数：8

共 18 条

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