Improving Yield and Reliability of Chip Multiprocessors

被引:0
作者
Pan, Abhisek [1 ]
Khan, Omer [1 ]
Kundu, Sandip [1 ]
机构
[1] Univ Massachusetts, Amherst, MA 01003 USA
来源
DATE: 2009 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION, VOLS 1-3 | 2009年
关键词
yield; reliability; micorarchitecture; multiprocessors;
D O I
暂无
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
An increasing number of hardware failures can be attributed to device reliability problems that cause partial system failure or shutdown. In this paper we propose a scheme for improving reliability of a homogeneous chip multiprocessor (CMP) that also serves to improve manufacturing yield. Our solution centers on exploiting the natural redundancy that already exists in multi-core systems by using services from other cores for functional units that are defective in a faulty core. A micro-architectural modification allows a core on a CMP to use another core as a coprocessor to service any instruction that the former cannot execute correctly. This service is accessed to improve yield and reliability, but at the cost of some loss of performance. In order to quantify this loss we have used a cycle-accurate simulator to simulate the performance of a dual-core system with one or two cores sustaining partial failure. Our results indicate that when a large and sparingly-used unit such as a floating point arithmetic unit fails in a core, even for a floating point intensive benchmark, we can continue to run each faulty core with help from companion cores with as little as 10% impact to performance and less than 1% area overhead.
引用
收藏
页码:490 / 495
页数:6
相关论文
共 50 条
[41]   Fault Leveling Techniques for Yield and Reliability Enhancement of NAND Flash Memories [J].
Shyue-Kung Lu ;
Shang-Xiu Zhong ;
Masaki Hashizume .
Journal of Electronic Testing, 2018, 34 :559-570
[42]   Yield and Reliability Improvement Techniques for Emerging Nonvolatile STT-MRAM [J].
Kang, Wang ;
Zhang, Liuyang ;
Zhao, Weisheng ;
Klein, Jacques-Olivier ;
Zhang, Youguang ;
Ravelosona, Dafine ;
Chappert, Claude .
IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, 2015, 5 (01) :28-39
[43]   Chip on glass (COG) technology and its reliability [J].
Kim, SI ;
Kang, S .
1997 INTERNATIONAL SYMPOSIUM ON MICROELECTRONICS, PROCEEDINGS, 1997, 3235 :476-481
[44]   Board level reliability of chip scale packages [J].
Hung, SC ;
Zheng, PJ ;
Chen, HN ;
Lee, SC ;
Lee, JJ .
1999 INTERNATIONAL SYMPOSIUM ON MICROELECTRONICS, PROCEEDINGS, 1999, 3906 :571-580
[45]   Board level reliability of chip scale packages [J].
Wang, ZP ;
Tan, YM ;
Chua, KM .
1998 INTERNATIONAL SYMPOSIUM ON MICROELECTRONICS, 1998, 3582 :513-518
[46]   Silicone, chip scale package, and its reliability [J].
Lee, YJ .
FIFTH ANNUAL PAN PACIFIC MICROELECTRONICS SYMPOSIUM, PROCEEDINGS, 2000, :345-353
[47]   Conceptual Approach to Improving Road Safety by Improving Reliability of Equipment [J].
Arifullin, Ilya .
12TH INTERNATIONAL CONFERENCE - ORGANIZATION AND TRAFFIC SAFETY MANAGEMENT IN LARGE CITIES SPBOTSIC-2016, 2017, 20 :21-24
[48]   Reliability of Sintered and Soldered High Power Chip Size Packages and Flip Chip LEDs [J].
Hanss, Alexander ;
Schmid, Maximilian ;
Bhogaraju, Sri Krishna ;
Conti, Fosca ;
Elger, Gordon .
2018 IEEE 68TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2018), 2018, :2080-2088
[49]   Reliability Evaluation of CIF (chip-in-flex) and COF (chip-on-flex) packages [J].
Jang, Jae-Won ;
Suk, Kyoung-Lim ;
Paik, Kyung-Wook ;
Lee, Soon-Bok .
FOURTH INTERNATIONAL CONFERENCE ON EXPERIMENTAL MECHANICS, 2010, 7522
[50]   Effects of underfill delamination and chip size on the reliability of solder bumped flip chip on board [J].
Lau, JH ;
Lee, SWR ;
Ouyang, C .
1999 INTERNATIONAL SYMPOSIUM ON MICROELECTRONICS, PROCEEDINGS, 1999, 3906 :592-598