A novel isolation-scaling technology for NAND EEPROMs with the minimized program disturbance

被引：26

作者：

Satoh, S ^{[1
]}

Hagiwara, H ^{[1
]}

Tanzawa, T ^{[1
]}

Takeuchi, K ^{[1
]}

Shirota, R ^{[1
]}

机构：

[1] Toshiba Corp, Microelect Engn Lab, Isogo Ku, Yokohama, Kanagawa 235, Japan

来源：

INTERNATIONAL ELECTRON DEVICES MEETING - 1997, TECHNICAL DIGEST | 1997年

关键词：

D O I：

10.1109/IEDM.1997.650384

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes the key technology to realize a scaled NAND EEPROM with the minimized-program disturbance. It has been clarified for the first time that the program disturbance caused by neighboring cells is drastically improved by reducing the field implantation dose. The limitation of conventional LOCOS width is estimated to be about 0.56um. Moreover, a careful device design and an optimization of the bottom implantation are essential in a advanced STI cell.

引用

页码：291 / 294

页数：4