Power-Aware FPGA Packing Algorithm

被引：1

作者：

Yang, M. ^{[1
]}

Xu, Hongying ^{[2
]}

Almaini, A. E. A. ^{[3
]}

机构：

[1] Fudan Univ, State Key Lab ASIC & Syst, Dept Microelect, Shanghai, Peoples R China

[2] Napier Univ, Edinburgh, Midlothian, Scotland

[3] Napier Univ, Sch Engn, Edinburgh, Midlothian, Scotland

来源：

2009 IEEE 8TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS | 2009年

关键词：

FPGA; Power dissipation; EDA; Algorithm;

D O I：

10.1109/ASICON.2009.5351571

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Field-Programmable Gate Array (FPGA) packing is one of abstraction levels in the FPGA CAD design flow which is aimed to pack logic components into clusters. As a result, the cluster-based FPGA can significantly improve timing, routability and power consumption as well. This paper proposes a novel packing algorithm using priori wire length estimation before actual routing taken apart. In addition, global placement was taken apart before packing to have additional placement information, which is also guided for the algorithm to selectively pack closely related module into one cluster. Experimental results show that power aware packing algorithm achieves 5% power reduction on average compared to traditional algorithm(1).

引用

页码：817 / +

页数：2