The Design of Multiplier in Integrated Circuit based on Low-power Algorithm

With rapid development of integrated circuit technologies, power consumption has been a key factor for long time, beside speed and area. Currently, in order to obtain the optimal low power result, we try to reduce system power consumption in each stage of integrated circuit design. Base on the traditional methodologies, a dual optimization methodology is developed, which reduces not only the number of addition operations, but also the width of one multiplier. From implementation point of view, the result of first optimization can be used for the second one, such implementation save the computation effort of second optimization, and promote operation speed and efficiency of whole methodology. The dissertation develop the low power technique for multipliers in different stages, it has reference value to integrated circuit front-end low power design for fixed coefficient multipliers.