Low-Power Design Methodology for CML and ECL Circuits

被引：0

作者：

Schrape, Oliver ^{[1
]}

Appel, Markus ^{[2
]}

Winkler, Frank ^{[2
]}

Krstic, Milos ^{[1
]}

机构：

[1] IHP, Technol Pk 25, D-15236 Frankfurt, Germany

[2] Humboldt Univ, D-10099 Berlin, Germany

来源：

2014 24TH INTERNATIONAL WORKSHOP ON POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION (PATMOS) | 2014年

关键词：

Design Methodology; Emitter Coupled Logic; ECL; CML; Current Mode Logic; Low Power;

D O I：

暂无

中图分类号：

TE [石油、天然气工业]; TK [能源与动力工程];

学科分类号：

0807 ; 0820 ;

摘要：

This paper presents a design methodology to enable the design of power efficient, high-speed CML/ECL circuits. It covers library requirements as well as proposed architectural improvements for power optimization. At transistor level, a voltage supply reduction from 3.3V to 2.5V is enabled by modifying classical three-level stack CML latch topology. Secondly, implementing several speed classes using different load resistor variants of most important gates allows for more efficient balancing of critical paths. The methodology is exemplary demonstrated on an 4:1 Serializer with 2 times 2x4 bit FIFO designed in low-cost 0.25 mu m SiGe BiCMOS process. AMS schematic simulation results show that both approaches lead to a reduction of the overall current of 39% to 58.68 mA, resulting in a total power dissipation of 146.70mW. The maximal data rate of 12.5 Gb/s is achieved, whereas 54% of the total power could be saved compared to baseline 3.3V design.

引用

页数：5

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