A 19.1% PAE, 22.4-dBm 53-GHz Parallel Power Combining Power Amplifier with Stacked-FET Techniques in 90-nm CMOS

被引：9
|
作者：
Sun, Wei-Che [1 ]
Kuo, Chien-Nan [1 ]
机构：
[1] Natl Chiao Tung Univ, Dept Elect Engn, Hsinchu 30010, Taiwan
来源：
2019 IEEE MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM (IMS) | 2019年
关键词：
amplifiers; CMOS; millimeter wave; power amplifiers; power combiner; transformers; stacked transistors; TRANSFORMER;
D O I：
10.1109/mwsym.2019.8701022
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A two-stage fully integrated 53-GHz stacked-FET power amplifier (PA) is implemented in 90-nm bulk CMOS. The output stage is optimized to achieve high output power while maintaining high power added efficiency (PAE). The complete PA achieves a measured saturated output power of 22.4 dBm and the 19.1% PAE at 2.4 V supply. It has -3 dB bandwidth of 8.8 GHz.
引用
收藏
页码：327 / 330
页数：4
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