Insulation Characteristics of GIS Epoxy Insulators with Non-uniform Surface Resistance under DC Voltage

Now that gas-insulated switchgear (GIS) for ac systems are becoming increasingly compact as specifications are rationalized, more consideration of their insulation characteristics for residual dc voltage is required. Furthermore, with dc power transmission technology drawing more and more global attention, clarifying the insulation characteristics of GIS for dc voltage is increasingly important. For GIS insulating epoxy spacer, the present paper experimentally and analytically studied the influence of spacer surface condition on dc withstand voltage performance. In specific terms, initially, an insulating spacer model with an area of non-uniform resistivity present in the surface layer was created and the dc voltage breakdown characteristics were obtained. As a result, it was clarified that the time delay to breakdown increased with lowering the applied voltage, or in other words, even if a low voltage was applied, breakdown may occur after an extended period. Subsequently, using the same non-uniform resistivity model, the change in the electric field distribution over time under dc voltage was investigated through transient electric field analysis. Consequently, it was found that the electric field distribution varied from a capacitive to a resistive field and the maximum electric field was generated in the boundary between the high-and low-resistivity areas. It was further clarified, based on these breakdown characteristics and electric field analytical results, that the presence of an area of non-uniform resistivity on the insulating spacer creepage surface caused electric field concentration over time and breakdown occurred if the electric field in the creepage surface direction exceeded 40 kV/mm or so. Moreover, the breakdown characteristics were investigated where a lightning impulse voltage was superimposed over a dc voltage. Consequently, the creepage breakdown electric field where a dc voltage was applied alone was almost identical to that where the superimposed voltage was applied. It means that the application of the superimposed voltage may potentially allow the insulating spacer withstand voltage performance to be evaluated by a shorter time test for a dc voltage alone or the dc voltage with a superimposed VFTO.