A Review on SRAM Memory Design Using FinFET Technology

被引:1
|
作者
Lakshmi, T. Venkata [1 ]
Kamaraju, M. [2 ]
机构
[1] Gudlavalleru Engn Coll, Vijayawada, Andhra Pradesh, India
[2] Gudlavalleru Engn Coll, Dept Elect & Commun Engn, AS&A, Vijayawada, Andhra Pradesh, India
关键词
CMOS; FinFET; Short Channel Effect; SRAM; Static Noise Margin; LOW-POWER; DEVICES; SYSTEM; IMPACT; ENERGY; CELL;
D O I
10.4018/IJSDA.302665
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
An innovative technology named FinFET (fin field effect transistor) has been developed to offer better transistor circuit design and to compensate the necessity of superior storage system (SS). As gate loses control over the channel, CMOS devices face some major issues like increase in manufacturing cost, less reliability and yield, increase of ON current, short channel effects (SCEs), increase in leakage currents, etc. However, it is necessary for the memory to have less power dissipation, short access time, and low leakage current. The traditional design of SRAM (static RAM) using CMOS technology represents severe performance degradation due to its higher power dissipation and leakage current. Thus, a nano-scaled device named FinFET is introduced for designing SRAM since it has threedimensional design of the gate. FinFET has been used to improve the overall performance and has been chosen as a transistor of choice because it is not affected by SCEs. In this work, the researchers have reviewed various FinFET-based SRAM cells, performance metrics, and the comparison over different technologies.
引用
收藏
页数:21
相关论文
共 50 条
  • [31] Independent-Double-Gate FinFET SRAM Technology
    Endo, K.
    O'uchi, S.
    Matsukawa, T.
    Liu, Y.
    Masahara, M.
    DIELECTRIC MATERIALS AND METALS FOR NANOELECTRONICS AND PHOTONICS 10, 2012, 50 (04): : 193 - 199
  • [32] SRAM and Single Device Isolation analysis in FinFET Technology
    Zhang, Yijun
    Tan, Li
    Li, Yu
    2020 CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE 2020 (CSTIC 2020), 2020,
  • [33] Statistical Variability and Reliability and the Impact on Corresponding 6T-SRAM Cell Design for a 14-nm Node SOI FinFET Technology
    Wang, Xingsheng
    Cheng, Binjie
    Brown, Andrew R.
    Millar, Campbell
    Kuang, Jente B.
    Nassif, Sani
    Asenov, Asen
    IEEE DESIGN & TEST, 2013, 30 (06) : 18 - 28
  • [34] A New 6T SRAM Memory Cell Based on FINFET Process
    Ma, Yaqi
    Zhang, Lijun
    Liu, Jinchen
    2020 THE 5TH IEEE INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUITS AND MICROSYSTEMS (ICICM 2020), 2020, : 251 - 254
  • [35] Operation-Aware Assist Circuit Design for Improved Write Performance of FinFET based SRAM
    Prajapati, Ekta
    Yadav, Nandakishor
    Pattanaik, Manisha
    Sharma, G. K.
    18TH INTERNATIONAL SYMPOSIUM ON VLSI DESIGN AND TEST, 2014,
  • [36] FinFET SRAM Process Technology for hp32 nm node and beyond
    Yagishita, Atsushi
    2007 IEEE International Conference on Integrated Circuit Design and Technology, Proceedings, 2007, : 59 - 62
  • [37] Design of Sram Architecture with Low Power without Affecting Speed Using Finfet
    Mohammed Sulaiman, S.
    Jaison, B.
    Anto Bennet, M.
    Vijay, M.
    Pandi Selvam, V.
    Anandakumar, P.
    INTERNATIONAL JOURNAL ON SMART SENSING AND INTELLIGENT SYSTEMS, 2022, 10 (05): : 295 - 310
  • [38] A robust and low-power near-threshold SRAM in 10-nm FinFET technology
    Ensan, Sina Sayyah
    Moaiyeri, Mohammad Hossein
    Hessabi, Shaahin
    ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2018, 94 (03) : 497 - 506
  • [39] SRAM Design in Fully-Depleted SOI Technology
    Nikolic, Borivoje
    Shin, Changhwan
    Cho, Min Hee
    Sun, Xin
    Liu, Tsu-Jae King
    Nguyen, Bich-Yen
    2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, 2010, : 1707 - 1710
  • [40] FinFET based SRAM bitcell design for 32 nm node and below
    Song, S. C.
    Abu-Rahma, M.
    Yeap, G.
    MICROELECTRONICS JOURNAL, 2011, 42 (03) : 520 - 526