Jitter characteristic in resonant clock distribution

被引：0

作者：

Mesgarzadeh, Behzad ^{[1
]}

Hansson, Martin ^{[1
]}

Alvandpour, Atila ^{[1
]}

机构：

[1] Linkoping Univ, Dept Elect Engn, S-58183 Linkoping, Sweden

来源：

ESSCIRC 2006: PROCEEDINGS OF THE 32ND EUROPEAN SOLID-STATE CIRCUITS CONFERENCE | 2006年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a detailed clock jitter characteristic analysis of a fully integrated 1.5-GHz resonant clocking fabricated in 130-nm CMOS, with 57% total clock power saving, compared to the conventional clocking implemented in the same test-chip. The jitter measurement result is in good agreement with the jitter analysis. Furthermore, a jitter-suppression technique based on injection locking phenomenon has been utilized to reduce the clock jitter and to solve the jitter peaking problem. Measurements show about 50% peak-to-peak clock jitter reduction from 28.4 ps to 14.5 ps after the activation of the injection locking.

引用

页码：464 / +

页数：2

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