Design and characterization of a p plus /n-well SPAD array in 150nm CMOS process

This paper reports on characterization results of a single-photon avalanche diode (SPAD) array in standard CMOS 150nm technology. The array is composed by 25 (5 x 5) SPADs, based on p+/n-well active junction along with a retrograde deep n-well guard ring. The square-shaped SPAD has a 10 mu m active diameter and 15.6 mu m pitch size, achieving a 39.9% array fill factor. Characterization results show a good breakdown voltage uniformity (40mV max-min) within each chip and 17mV/degrees C temperature coefficient. The median DCR is 0.4Hz/mu m2, and the afterpulsing probability is 0.85% for a dead time of 150ns at 3V excess bias voltage. The peak PDP is 31% at 450nm wavelength and a good uniformity (1.1% standard deviation) is observed for the array at 5V excess bias. The single SPADs exhibit a timing jitter of 52ps (FWHM) and 42ps (FWHM) under a 468-nm and a 831-nm laser, respectively. The crosstalk probability as a function of pixel-to-pixel distance and excess bias voltage is presented, and random telegraph signal (RTS) noise is also discussed in detail. (C) 2017 Optical Society of America