An Accurate and Efficient Stochastic Computing Adder Exploiting Bit Shuffle Control Scheme

Stochastic computing is an emerging computing paradigm. With the use of a simple logic gate, SC can perform arithmetic operations, resulting in a small and low-power design. In this paper, we present an SC adder with one RNG and shuffling operation to improve the accuracy of the operation results. With a 65-nm CMOS technology, the proposed SC adder improves in terms of area, power, and energy by 25.5%, 27.62%, and 23.67%, respectively compared to the conventional SC adder. Additionally, the proposed SC adder improves the MAE and MSE by 1.8 ' and 3.3 ', respectively, compared to the conventional counterpart.