A Study on the Assertion-Based Verification of Digital IC

被引：1

作者：

Li, Yangyang ^{[1
]}

Wu, Wuchen ^{[1
]}

Hou, Ligang ^{[1
]}

Cheng, Hao ^{[2
]}

机构：

[1] Beijing Univ Technol, VLSI & Syst Lab, Beijing, Peoples R China

[2] Zhengzhou Univ, Elect Engn Coll, Zhengzhou, Peoples R China

来源：

ICIC 2009: SECOND INTERNATIONAL CONFERENCE ON INFORMATION AND COMPUTING SCIENCE, VOL 2, PROCEEDINGS: IMAGE ANALYSIS, INFORMATION AND SIGNAL PROCESSING | 2009年

关键词：

Observability; Assertion-Based Verification; System Verilog Assertion; UART;

D O I：

10.1109/ICIC.2009.114

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

Verification plays more and more important role in complex VLSI design. It has two main challenges: one is to insure that the input stimulus can control the function spots inside the design; the other is to insure the errors can be observed from the design output. This paper presents an easy approach of assertion-based verification (ABV) method by dividing it into five steps, through which we embed assertions in source codes to monitor key functional spots of the design during simulation. As an application example, a case study of functional verification for a UART model, using System Verilog Assertion (SVA), is provided. The studied result shows that the new method is feasible and can be applied in the design and verification process to increase the observability of the design.

引用

页码：25 / +

页数：2

共 6 条

[1]

[Anonymous], 18002005 IEEE

[2]

FOSTER H, 2006, INTEGRATING FORMAL V

[3] I'm done simulating; Now what? Verification coverage analysis and correctness checking of the DECchip 21164 alpha microprocessor [J].

Kantrowitz, M ;

Noack, LM .

33RD DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 1996, 1996, :325-330

[4]

PING YU, 2007, APPL ASSERTION BASED

[5]

Vijayaraghavan S., 2006, PRACTICAL GUIDE SYST

[6]

Ziv A, 2003, DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, PROCEEDINGS, P834

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