A Low-Power Reduced Kick-Back Comparator with Improved Calibration for High-Speed Flash ADCs

被引：1

作者：

Torfs, Guy ^{[1
]}

Li, Zhisheng ^{[1
]}

Bauwelinck, Johan ^{[1
]}

Yin, Xin ^{[1
]}

Vandewege, Jan ^{[1
]}

Van Der Plas, Geert ^{[2
]}

机构：

[1] Univ Ghent, Dept Informat Technol, Ghent, Belgium

[2] IMEC, Leuven, Belgium

来源：

IEICE TRANSACTIONS ON ELECTRONICS | 2009年 / E92C卷 / 10期

关键词：

comparator; kick-back; calibration; low-power; flash ADC;

D O I：

10.1587/transele.E92.C.1328

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A novel low-power kick-back reduced comparator for use in high-speed flash analog-to-digital converters (ADC) is presented. The proposed comparator combines cascode transistors to reduce the kick-back noise with a built-in threshold voltage to remove the static power consumption of a reference. Without degrading other figures, the kick-back noise is reduced by a factor 8, compared to a previous design without cascode transistors. An improved calibration structure is also proposed to improve linearity when used in an ADC. Simulated in a standard CMOS technology the comparator consumes 106.5 mu W at 1.8 V power supply and 1 GHz clock frequency.

引用

页码：1328 / 1330

页数：3

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