Delay and power expressions for a CMOS inverter driving a resistive-capacitive load

被引：37
作者：
Adler, V
Friedman, EG
机构：
[1] University of Rochester,Department of Electrical Engineering
来源：
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING | 1997年 / 14卷 / 1-2期
关键词：
interconnect; CMOS inverter model; interconnect delay; power dissipation; short-circuit power;
D O I：
10.1023/A:1008282308028
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A delay and power model of a CMOS inverter driving a resistive-capacitive load is presented. The model is derived from Sakurai's alpha-power law and exhibits good accuracy. The model can be used to design and analyze those CMOS inverters that drive a large RC load when considering both speed and power. Expressions are provided for estimating the propagation delay and transition time which exhibit less than 27% discrepancy from SPICE for a wide variety of RC loads. Expressions are also provided for modeling the short-circuit power dissipation of a CMOS inverter driving a resistive-capacitive interconnect line which are accurate to within 15% of SPICE for most practical loads.
引用
收藏
页码：29 / 39
页数：11
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