Layout parasitic limitations in high-speed circuits

The exponential growth of microelectronics, allowing a tenfold increase of circuit complexity nearly every five years, constantly presents new challenges to the IC designer. The physical and dynamic characteristics of wires on a die begin to dictate the topology of an integrated circuit. Second- and third-order effects are becoming important in designs built on processes smaller than 400 nm. In the first part we try to illustrate the standard mechanism of parasitic extraction while in the second part we present the influence of the parasitic layout elements on the performance of a limiting amplifier used in the optic fibre transceivers.