Regular {4,8} LDPC codes and their low error floors

Regular LDPC codes are a special class of lowdensity codes having an equal number of ones in each row and column of the parity check matrix describing the linear code. The uniform structure of regular LDPC codes allows a practical hardware implementation which can efficiently utilize the inherent parallelism of the message passing algorithm (MPA) commonly used to decode low-density codes. The class of {3, 6} LDPC codes has been extensively studied and they have been proven to provide very good error performance, especially at lower SNR. {4,8} codes have not been analyzed nearly as much in the literature, mainly because their 'threshold,' the SNR where the waterfall region of the error performance curve begins, is typically a quarter of a dB or so worse than for comparable-length {3, 6} codes. It has been proposed that {4,8} codes have better high SNR behavior, but until recently it was not possible to verify this conjecture. A new technique which can efficientlyfind errorfloors of LDPC codes now has the ability to illuminate just how good {4, 8} codes are in the high SNR region - a result which is of great interest for many practical applications. This paper will analyze the error floor characteristics of some {4, 8} codes and provide a simple algorithm for designing {4, 8} codes with low error floors. A newly-designed rate112 (1200,600) {4,8} code with a vastly superior error floor compared to codes of similar parameters is introduced.