A Fabrication Process for Emerging Nanoelectronic Devices Based on Oxide Tunnel Junctions

被引：3

作者：

Drouin, Dominique ^{[1
,2
]}

Droulers, Gabriel ^{[1
,2
]}

Labalette, Marina ^{[1
,2
]}

Sang, Bruno Lee ^{[1
,2
]}

Harvey-Collard, Patrick ^{[3
]}

Souifi, Abdelkader ^{[4
]}

Jeannot, Simon ^{[5
]}

Monfray, Stephane ^{[5
]}

Pioro-Ladriere, Michel ^{[3
,6
]}

Ecoffey, Serge ^{[1
,2
]}

机构：

[1] Univ Sherbrooke, 3IT, 3000 Boul Univ, Sherbrooke, PQ J1K 0A5, Canada

[2] Univ Sherbrooke, LN2, CNRS UMI 3463, 3000 Boul Univ, Sherbrooke, PQ J1K 0A5, Canada

[3] Univ Sherbrooke, Dept Phys, 2500 Boul Univ, Sherbrooke, PQ J1K 2R1, Canada

[4] UMR CNRS 5270, INSA, INL, 7 Ave Jean Capelle, F-69621 Villeurbanne, France

[5] STMicroelectronics, F-38926 Crolles, France

[6] Canadian Inst Adv Res, Toronto, ON M5G 1Z8, Canada

来源：

JOURNAL OF NANOMATERIALS | 2017年 / 2017卷

基金：

加拿大自然科学与工程研究理事会;

关键词：

SINGLE-ELECTRON TRANSISTOR;

D O I：

10.1155/2017/8613571

中图分类号：

TB3 [工程材料学];

学科分类号：

0805 ; 080502 ;

摘要：

We present a versatile nanodamascene process for the realization of low-power nanoelectronic devices with different oxide junctions. With this process we have fabricated metal/insulator/metal junctions, metallic single electron transistors, silicon tunnel field effect transistors, and planar resistive memories. These devices do exploit one or two nanometric-scale tunnel oxide junctions based on TiO2, SiO2, HfO2, Al2O3, or a combination of those. Because the nanodamascene technology involves processing temperatures lower than 300 degrees C, this technology is fully compatible with CMOS back-end-of-line and is used for monolithic 3D integration.

引用

页数：8

共 26 条

[1] Emerging memories [J].