IP core design of harmonic detection algorithm for power system

被引：0
|
作者：
Yang, Chao [1 ]
Jiang, Liang [1 ]
Sun, Peng [2 ]
机构：
[1] Nanjing Inst Ind Technol, Sch Elect Engn, Nanjing, Peoples R China
[2] China Mobile Commun Grp Design Inst Co Ltd, Heilongjiang Branch, Harbin, Peoples R China
来源：
PROCEEDINGS OF 2020 IEEE 5TH INFORMATION TECHNOLOGY AND MECHATRONICS ENGINEERING CONFERENCE (ITOEC 2020) | 2020年
关键词：
Power systems; Harmonic detection; IP core; Wavelet transform; Wavelet packet transformation;
D O I：
暂无
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
A large number of data operations in the common power system harmonic detection algorithm lead to master CPU run slower, which affects the accuracy and real-time performance of harmonic detection. A harmonic detection algorithm based on IP kernel is proposed. Under the condition that the data operation function of the original algorithm remains unchanged, this method completes the power system harmonic data analysis and processing operation by replacing the traditional main control CPU software program through the hardware logic unit, and solidifies the generated hardware description language file (VHDL) into the programmable logic device (FPGA) to create the IP core of the specific functions. Finally, the time taken by this method to process the same set of harmonic data is compared with the traditional software method. The results show that the method is effective and real-time.
引用
收藏
页码：275 / 278
页数：4
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