Quarc: a High-Efficiency Network on-Chip Architecture

被引：4

作者：

Moadeli, Mahmoud ^{[1
]}

Maji, Partha ^{[2
]}

Vanderbauwhede, Wim ^{[1
]}

机构：

[1] Univ Glasgow, Dept Comp Sci, Glasgow G12 8QQ, Lanark, Scotland

[2] Ins Syst Level Integrat, Livingston, Scotland

来源：

2009 INTERNATIONAL CONFERENCE ON ADVANCED INFORMATION NETWORKING AND APPLICATIONS | 2009年

关键词：

D O I：

10.1109/AINA.2009.64

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Th novel Quarc NoC architecture, inspired by the Spidergon scheme [5] is introduced as a NoC architecture that is highly efficient in performing collective communication operations including broadcast and multicast. The efficiency of the Quarc architecture is achieved through balancing the traffic which is the result of the modifications applied to the topology and the routing elements of the Spidergon NoC This paper provides an ASIC implementation of both architectures using UMC's 0.13 mu m CMOS technology and demonstrates an analysis and comparison of the cost and performance between the Quarc and the Spidergon NoCs.

引用

页码：98 / +

页数：2

共 15 条

[1] Coppola M, 2009, SYST-CHIP DES TECHNO, P1
[2] DALLOSSO M, 2003, INT C COMP DES
[3] Duato J., 2003, Interconnection networks
[4] AEthereal network on chip: Concepts, architectures, and implementations
Goossens, K
Dielissen, J
Radulescu, A
[J]. IEEE DESIGN & TEST OF COMPUTERS, 2005, 22 (05): : 414 - 421
[5] HU H, 1997, IEEE T PARALLEL DIST
[6] LIN X, 1998, J PARALLEL DISTRIBUT, P274
[7] LIU J, 2003, J SYSTEM ARCHITECTUR
[8] Lu ZH, 2006, IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, PROCEEDINGS, P205
[9] MILLBERG M, 2004, INT C VLSI DES
[10] MOADELI M, 2008, PAR DISTR SYST INT C

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