Self-referenced sense amplifier for across-chip-variation immune sensing in high-performance content-addressable memories

被引:22
作者
Arsovski, Igor [1 ]
Wistort, Reid [1 ]
机构
[1] IBM Corp, Silicon Solut, Essex Jct, VT 05452 USA
来源
PROCEEDINGS OF THE IEEE 2006 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2006年
关键词
D O I
10.1109/CICC.2006.320819
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A memory sense-amplifier self-calibrates during sense-line precharge to reduce the required signal development and minimize data capture timing uncertainty caused by random device variation. When compared to conventional single-ended sensing, this method reduces sense time by 70% and decreases sense-power by 40%. The self-referenced sensing scheme (SRSS) is used to implement the search operation in Content-Addressable Memory (CAM) testchip. Fabricated in 1V 65nm CMOS, this scheme achieves a 0.6ns search time on a 70bit sense-line while consuming only 0.99 fJ/bit/search. Measured search access time on a five bank 64x240bit ternary CAM including selective precharge is 2.2ns. Measured power consumption at 450MHz is 10mW. Hardware shows robust search operation over a voltage range of 0.6V to 1.7V.
引用
收藏
页码:453 / 456
页数:4
相关论文
共 7 条
[1]  
ARSOVSKI I, 2003, IEEE JSSC JAN
[2]   A 1-V 128-kb four-way set-associative CMOS cache memory using wordline-oriented tag-compare (WLOTC) structure with the content-addressable-memory (CAM) 10-transistor tag cell [J].
Lin, PF ;
Kuo, JB .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2001, 36 (04) :666-675
[3]  
MASUDA H, ISCAS 2005, V6, P5934
[4]  
MCLEOD M, 1982, EUR SOL STAT CIRC C
[5]   A design for high-speed low-power CMOS fully parallel content-addressable memory macros [J].
Miyatake, H ;
Tanaka, M ;
Mori, Y .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2001, 36 (06) :956-968
[6]  
ZUCHOWSKI PS, ICCAD 2004, P336
[7]  
ZUKOWSKI CA, 1997, GREAT LAK S VLSI, P83