A Vertical Solenoid Inductor for Noise Coupling Minimization in 3D-IC

被引：0

作者：

Yahalom, Gilad ^{[1
]}

Wang, Alice ^{[2
]}

Ko, Uming ^{[2
]}

Chandrakasan, Anantha ^{[1
]}

机构：

[1] MIT, 77 Massachusetts Ave, Cambridge, MA 02139 USA

[2] Mediatek, Hsinchu, Taiwan

来源：

PROCEEDINGS OF THE 2015 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS SYMPOSIUM (RFIC 2015) | 2015年

关键词：

radiofrequency integrated circuits; three-dimensional integrated circuits; voltage-controlled oscillators; inductors; electromagnetic coupling; phase noise;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents the use of an integrated solenoid inductor in three dimensional integrated circuits (3D-IC) for improved noise mitigation. The structure is fabricated in a two-tier, stacked 28nm CMOS using through silicon vias (TSV). The structure is implemented as part of an LC voltage-controlled oscillator (VCO), and exhibits 6dB improvement in phase noise and 14dB less coupling from adjacent digital clock lines compared to a planar two-turn inductor.

引用

页码：55 / 58

页数：4

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