Concurrent error detection of fault-based side-channel cryptanalysis of 128-bit RC6 block cipher

被引：4

作者：

Wu, KJ ^{[1
]}

Mishra, P ^{[1
]}

Karri, R ^{[1
]}

机构：

[1] Polytech Univ, ECE Dept, Metrotech Ctr 6, Brooklyn, NY 11201 USA

来源：

MICROELECTRONICS JOURNAL | 2003年 / 34卷 / 01期

关键词：

concurrent error detection; cryptanalysis; RC6 block cipher; FPGA;

D O I：

10.1016/S0026-2692(02)00126-X

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Fault-based side channel cryptanalysis is very effective against symmetric and asymmetric encryption algorithms. Although straightforward hardware and time redundancy based concurrent error detection (CED) architectures can be used to thwart such attacks, they entail significant overhead (either area or performance). In this paper we investigate two systematic approaches to low-cost, low-latency CED for symmetric encryption algorithm RC6. The proposed techniques have been validated on FPGA implementations of RC6, one of the advanced encryption standard finalists. (C) 2002 Elsevier Science Ltd. All rights reserved.

引用

页码：31 / 39

页数：9

共 16 条

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