Analysis of the impact of bus implemented EDCs on on-chip SSN

被引：0

作者：

Rossi, Daniele ^{[1
]}

Steiner, Carlo ^{[1
]}

Metra, Cecilia ^{[1
]}

机构：

[1] Univ Bologna, DEIS, Viale Risorgimento 2, I-40136 Bologna, Italy

来源：

2006 DESIGN AUTOMATION AND TEST IN EUROPE, VOLS 1-3, PROCEEDINGS | 2006年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper we analyze the impact of error detecting codes, implemented on an on-chip bus, on the on-chip simultaneous switching noise (SSN). First, we analyze in detail how SSN is impacted by different bus transitions, pointing out its dependency on the number and placement of switching wires. Afterwards, we present an analytical model that we have developed in order to estimate the SSN, and that we prove to be very accurate in SSN prediction. Finally, by employing the developed model, we estimate the SSN due to different EDCs implemented on an on-chip bus. In particular we highlight how their differences in the number of switching wires, bus parallelism and codewords influence the on-chip SSN.

引用

页码：57 / +

页数：2

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