Design and Analysis of CMOS Frequency Dividers With Wide Input Locking Ranges

被引:41
作者
Chen, Chung-Chun [1 ,2 ]
Tsao, Hen-Wai [1 ,2 ]
Wang, Huei [1 ,3 ]
机构
[1] Natl Taiwan Univ, Dept Elect Engn, Taipei 10617, Taiwan
[2] Natl Taiwan Univ, Grad Inst Elect Engn, Taipei 10617, Taiwan
[3] Natl Taiwan Univ, Grad Inst Commun Engn, Taipei 10617, Taiwan
关键词
CMOS; injection-locked frequency dividers (ILFDs); millimeter-wave (MMW); phase-locked loop (PLL); voltage-controlled oscillator (VCO); wide locking range;
D O I
10.1109/TMTT.2009.2033239
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A millimeter-wave (MMW) frequency synthesizer needs a low-power frequency divider (FD) with a wide input locking range to ensure reliability and lower power operation. In this paper, the design and analysis of low-power wide locking range MMW FDs are presented. Proposed are two divide-by-2 (D2) and divide-by-4 (D4) FDs that achieve the widest locking range reported to date by using a dual-mixing technique. Both FDs are fabricated in 90-nm CMOS and are demonstrated to achieve very wide input locking ranges without any tuning mechanism. At an input power of 0 dBm, the D2 FD has a locking range of 51-74 GHz, and that of the D4 FD is 82.5-89 GHz. The power consumption is only 3 mW for both the D2 FD and the D4 FD, from a 0.5 V supply. The proposed D2 and D4 FDs may facilitate incorporation into a product of a MMW phase-locked loop that is smaller, consumes less power, and is more reliable than the conventional approach.
引用
收藏
页码:3060 / 3069
页数:10
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