Active harmonic load-pull for on-wafer out-of-band device linearity optimization

In this paper, we present an active harmonic load-pull system especially developed for the on-wafer linearity characterization/optimization of active devices with wideband modulated signals using the out-of-band linearization technique. Our setup provides independent control of the impedances at the baseband, fundamental, and second-harmonic frequencies presented to the input and output of the device under test. Furthermore, to enable realistic test conditions with wideband-modulated signals, the electrical delays in the load-pull system are kept as small as possible by implementing a novel loop architecture with in-phase quadrature modulators. We have achieved a phase variation of the reflection coefficient of only 5 degrees/MHz for both the fundamental and second-harmonic frequencies. We demonstrate the high potential of the system for the on-wafer evaluation of new technology generations by applying out-of-band linearization to heterojunction bipolar transistor (HBT) and laterally diffused metal-oxide-semiconductor (LDMOS) devices. For the HBT, we outline a game plan to obtain the optimum efficiency-linearity tradeoff. Finally, a record-high efficiency-linearity tradeoff was achieved (without digital predistortion) for an inverse class-AB operated Philips Gen 6 LDMOS device, yielding 44% efficiency at an adjacent channel power level of -45 dBc at 2.14 GHz for an IS-95 signal.