Ultra Low power Dissipation in 9T SRAM Design by Using FinFET Technology

Rapid growth of semiconductor industries demanded for lower power consumption for recent IC design in Deep sub micron technology (DSM). As steady miniaturization of transistor technology is emerging, has yielded a progressive up gradation in digital circuits performance. But with this compact circuitry a significant challenges have also been seen Short channel effect (SCE) and Drain induced barrier lowering effects (DIBL). In this paper FinFET technology is used for SRAM cells in different topology and a proposed 9T SRAM cell is analysed with the other (N) T SRAM cells. The proposed circuit shows maximum saving of dynamic power in SG and LP is to 82.21% and 90.57% in 10T, maximum leakage power saving in SG and LP mode is 57.53%, 61.35% at 25 degrees C and 45.13%, 48.52 at 110 degrees C in 9T SRAM. Simulation is done by using HSPICE at 32nm with V-DD = 0.8V for fair comparison of results.