A low-noise low-drift transducer ADC

An analog-to-digital converter (ADC) is described that takes the output from a load-cell transducer directly and performs amplification and signal-conditioning as well as high-resolution conversion. A very low offset drift of 10 nV/degrees C is achieved by a chop mode that includes the entire analog signal path. This chop mode adapts easily to de or ac excitation of the load-cell resistor bridge. An input-referred noise of 31 nV rms is achieved on a 10 mV signal in a 2 Hz bandwidth while employing a purely CMOS switched-capacitor design. The digital low-pass Alter, as well as removing chopped offset, has a special anode that enables it to rapidly track step changes in the input from the transducer. Finally, a gain calibration scheme is described that uses precision switched-capacitor attenuation of the 5 V reference voltage to provide an accurate near full-scale calibration voltage, consistent with the low-level input ranges of the converter. The gain drift is 2 ppm/degrees C and the power supply rejection (PSR) and common mode rejection (CMR) are 120 dB. The process used is 0.6-mu m double-poly double-metal (DPDM) CMOS and the die size is 2.73 x 4.68 mm.