SEU and SET of 65 Bulk CMOS Flip-flops and Their Implications for RHBD

被引:24
作者
Zhao, Yuanfu [1 ]
Wang, Liang [1 ]
Yue, Suge [1 ]
Wang, Dan [1 ]
Zhao, Xinyuan [1 ]
Sun, Yongshu [1 ]
Li, Dongqiang [1 ]
Wang, Fuqing [1 ]
Yang, Xiaoqian [1 ]
Zheng, Hongchao [1 ]
Ma, Jianhua [1 ]
Fan, Long [1 ]
机构
[1] Beijing Microelect Technol Inst, Beijing 100076, Peoples R China
关键词
Dual interlocked cell (DICE); flip-flop; radiation hardening by design (RHBD); redundant delay filter (RDF); single event transient (SET); single event upset (SEU); soft error; time domain analysis; HARDENED LATCH; DESIGN; TECHNOLOGY; DICE; ELEMENT; IMPACT;
D O I
10.1109/TNS.2015.2490552
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Two 65 nm bulk CMOS test chips, each containing several different types of flip-flop chains, are designed and tested. Heavy ion results are given and analyzed across ion LET and in proposed time domain. The single event upset (SEU) and single event transient (SET) performance of various DFFs are compared and discussed, concluding several practical implications for radiation hardening by design (RHBD). The effectiveness of redundant delay filter (RDF) on mitigating SETs is proven by experiment for the first time.
引用
收藏
页码:2666 / 2672
页数:7
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