Capacitance-Voltage (CV) Characterization of GaAs-Oxide Interfaces

被引:9
作者
Brammertz, G. [1 ]
Lin, H. C. [2 ]
Martens, K. [1 ]
Mercier, D. [1 ]
Merckling, C. [1 ]
Penaud, J. [3 ]
Adelmann, C. [1 ]
Sioncke, S. [1 ]
Wang, W. E. [4 ]
Caymax, M. [1 ]
Meuris, M. [1 ]
Heyns, M. [1 ,5 ]
机构
[1] IMEC VZW, Kapeldreef 75, B-3001 Louvain, Belgium
[2] Purdue Univ, Birck Nanotechnol Ctr, W Lafayette, IN 47907 USA
[3] Riber, F-95870 Bezons, France
[4] IMEC, Intel Assignee, B-3001 Leuven, Belgium
[5] Katholieke Univ Leuven, Dept Met & Mat Engn, B-3001 Leuven, Belgium
来源
PHYSICS AND TECHNOLOGY OF HIGH-K GATE DIELECTRICS 6 | 2008年 / 16卷 / 05期
关键词
D O I
10.1149/1.2981632
中图分类号
O646 [电化学、电解、磁化学];
学科分类号
081704 ;
摘要
We will shortly review the basic physics of charge carrier trapping and emission from trapping states within the bandgap of a semiconductor in order to show that high temperature CV-measurements are necessary for GaAs MOS characterization. The mid-gap trapping states in GaAs have characteristic emission times of the order of 1000 seconds, which makes them extremely complicated to measure at room temperature. Higher substrate temperatures speed up these emission times, which makes measurements of the mid-gap traps possible with standard CV-measurements. CV-characterizations of GaAs/Al2O3, GaAs/Gd2O3, GaAs/HfO2 and In0.15Ga0.85As/Al2O3 interfaces show the existence of four interface state peaks, independent of the gate oxide deposited: a hole trap peak close to the valence band, a hole trap peak close to mid-gap energies, an electron trap peak close to mid-gap energies and an electron trap peak close to the conduction band.
引用
收藏
页码:507 / +
页数:2
相关论文
共 10 条
[1]   Characteristic trapping lifetime and capacitance-voltage measurements of GaAs metal-oxide-semiconductor structures [J].
Brammertz, Guy ;
Martens, Koen ;
Sioncke, Sonja ;
Delabie, Annelies ;
Caymax, Matty ;
Meuris, Marc ;
Heyns, Marc .
APPLIED PHYSICS LETTERS, 2007, 91 (13)
[2]   Deep-level effects in GaAs microelectronics: A review [J].
N. P. Khuchua ;
L. V. Khvedelidze ;
M. G. Tigishvili ;
N. B. Gorev ;
E. N. Privalov ;
I. F. Kodzhespirova .
Russian Microelectronics, 2003, 32 (5) :257-274
[3]  
LUTH H, 2001, SOLID SURFACES INTER, P343
[4]   On the correct extraction of interface trap density of MOS devices with high-mobility semiconductor substrates [J].
Martens, Koen ;
Chui, Chi On ;
Brammertz, Guy ;
De Jaeger, Brice ;
Kuzum, Duygu ;
Meuris, Marc ;
Heyns, Marc M. ;
Krishnamohan, Tejas ;
Saraswat, Krishna ;
Maes, Herman E. ;
Groeseneken, Guido .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2008, 55 (02) :547-556
[5]  
NICOLLIAN EH, 1981, MOS METAL OXIDE SEMI, P286
[6]  
Passlack M, 2005, MATERIALS FUNDAMENTALS OF GATE DIELECTRICS, P403, DOI 10.1007/1-4020-3078-9_12
[7]  
SCHRODER DK, 1990, SEMICONDUCTOR MAT DE, P297
[8]   STATISTICS OF THE RECOMBINATIONS OF HOLES AND ELECTRONS [J].
SHOCKLEY, W ;
READ, WT .
PHYSICAL REVIEW, 1952, 87 (05) :835-842
[9]   UNIFIED DEFECT MODEL AND BEYOND [J].
SPICER, WE ;
LINDAU, I ;
SKEATH, P ;
SU, CY .
JOURNAL OF VACUUM SCIENCE & TECHNOLOGY, 1980, 17 (05) :1019-1027
[10]   Submicrometer inversion-type enhancement-mode InGaAs MOSFET with atomic-layer-deposited Al2O3 as gate dielectric [J].
Xuan, Y. ;
Wu, Y. Q. ;
Lin, H. C. ;
Shen, T. ;
Ye, Peide D. .
IEEE ELECTRON DEVICE LETTERS, 2007, 28 (11) :935-938