Testing for Transistor Aging

被引：37

作者：

Baba, A. Hakan ^{[1
]}

Mitra, Subhasish ^{[1
]}

机构：

[1] Stanford Univ, Dept Elect Engn & Comp Sci, Stanford, CA 94305 USA

来源：

2009 27TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS | 2009年

关键词：

D O I：

10.1109/VTS.2009.56

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Transistor aging results in circuit delay degradation over time, and is a growing concern for future systems. On-line circuit failure prediction. together with on-line self-test, can overcome transistor aging challenges for robust systems with built-in self-healing. Effective circuit failure prediction requires very thorough testing Effective to estimate the amount of aging in various parts of a large design during system operation. This paper introduces such testing techniques. Results on large designs demonstrate the practicality and effectiveness of presented techniques.

引用

页码：215 / 220

页数：6

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