Chip Package Interaction (CPI) risk assessment of 22FDX® Wafer Level Chip Scale Package (WLCSP) using 2D Finite Element Analysis modeling

被引：3

作者：

Machani, Kashi Vishwanath ^{[1
]}

Kuechenmeister, Frank ^{[1
]}

Breuer, Dirk ^{[1
]}

Klewer, Christian ^{[1
]}

Cho, Jae Kyu ^{[2
]}

Young-Fisher, Kristina ^{[2
]}

机构：

[1] GLOBALFOUNDRIES Dresden Module One LLC & Co KG, Wilschdorfer Landstr 101, D-01109 Dresden, Germany

[2] GLOBALFOUNDRIES Inc, 400 Stone Break Rd Extens, Malta, NY 12020 USA

来源：

2020 IEEE 70TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2020) | 2020年

关键词：

CPI; WLCSP assembly; RDL; BEoL; ultralow-k ILD; FEM;

D O I：

10.1109/ECTC32862.2020.00177

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In order to address the Chip-Package Interaction (CPI) risks associated with the Wafer Level Chip Scale Package (WLCSP), GLOBALFOUNDRIES has developed Finite Element (FE) models to simulate the mechanical stress in the Backend of Line (BEoL) and Far Back End of Line (FBEoL) during mass reflow process. This paper discusses the CPI failure risk associated with WLCSP, modeled with and without the redistribution layers (RDL) introduction above the BEoL. The WLCSP model has been modified to assess the design variations within the RDL and the FBEoL. The paper also highlights the FE model verification between the two-dimensional (2D) versus the three-dimensional (3D) models and validation by comparing the simulation results to the experimental test data.

引用

页码：1100 / 1105

页数：6