Development of Novel Intermetallic Joints using Thin Film Indium Based Solder by Low Temperature Bonding Technology for 3D IC Stacking

被引:17
作者
Choi, Won Kyoung [1 ]
Premachandran, C. S. [1 ]
Chiew, Ong Siong [1 ]
Ling, Xie [1 ]
Ebin, Liao [1 ]
Khairyanto, Ahmad [1 ]
Ratmin, Bin [1 ]
Chen, Kelvin [1 ]
Sheng, Wei [1 ]
Thaw, Phyo Phyo [1 ]
Lau, John H. [1 ]
机构
[1] ASTAR, Inst Microelect, Singapore 117685, Singapore
来源
2009 IEEE 59TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE, VOLS 1-4 | 2009年
关键词
D O I
10.1109/ECTC.2009.5074036
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Low temperature bonding technology was developed using In-alloy on Au at a low temperature below 200 degrees C forming robust intermetallics (IMC) joints with high remelting temperature (>300 degrees C), so that after bonding, the IMC joints can withstand the subsequent processes without any degradation. Process parameters on the solder joint were optimized extensively in bonding and annealing process (temperature, time, and pressure). The joint fabricated at an optimal condition, which is 180 degrees C for 45sec followed by annealing at 120 degrees C for 12hrs, was evaluated in terms of microstructure and compositional observations by means of scanning electron microscope (SEM) and transmittance electron microscope (TEM). As a result, it was confirmed that the joint was completely occupied with the Au-In based IMC phases. And the re-melting temperature was measured as above 400 degrees C by using Differential Scanning Calorimetery (DSC) and Thermo-Mechanical Analysis (TMA). This IMC joint showed a high bonding shear strength (>20MPa) and a low electrical resistance (<100m Omega). Based on this study, the 3 stacked dice with 8x8 mm(2) dies with similar to 1700 I/Os of 80um solder bumps were fabricated in a chip to chip stacking method. It showed uniform bonding all over the die in each layer and the high bonding strength of similar to 40 MPa and passed the 3 times reflow test at 260 degrees C. The IMC joint reliability was examined. After going through the multiple reflows at 260 degrees C, the bonded samples exhibited no delaminating and no changes in the bonding strength and the electrical resistance.
引用
收藏
页码:333 / 338
页数:6
相关论文
共 13 条
[1]   Microstructure examination of copper wafer bonding [J].
Chen, KN ;
Fan, A ;
Reif, R .
JOURNAL OF ELECTRONIC MATERIALS, 2001, 30 (04) :331-335
[2]  
CHOI WK, 2008, P 58 EL COMP TECHN C, P1294
[3]  
FUKUSHIMA T, 2007, P 57 EL COMP TECHN C, P837
[4]   Vertical system integration by using inter-chip vias and solid-liquid interdiffusion bonding [J].
Klumpp, A ;
Merkel, R ;
Ramm, P ;
Weber, J ;
Wieland, R .
JAPANESE JOURNAL OF APPLIED PHYSICS PART 2-LETTERS & EXPRESS LETTERS, 2004, 43 (7A) :L829-L830
[5]  
LIU HS, 2003, J ELECT MAT, V32
[6]   On shock wave theory [J].
Liu, TP .
TAIWANESE JOURNAL OF MATHEMATICS, 2000, 4 (01) :9-20
[7]  
Mitsuhashi T, 2007, MATER RES SOC SYMP P, V970, P155
[8]   Three-dimensional wafer stacking via Cu-Cu bonding integrated with 65-nm strained-Si/low-k CMOS technology [J].
Morrow, P. R. ;
Park, C. -M. ;
Ramanathan, S. ;
Kobrinsky, M. J. ;
Harmes, M. .
IEEE ELECTRON DEVICE LETTERS, 2006, 27 (05) :335-337
[9]   3D chip stacking technology with low-volume lead-free interconnections [J].
Sakuma, K. ;
Andry, P. S. ;
Dang, B. ;
Maria, J. ;
Tsang, C. K. ;
Patel, C. ;
Wright, S. L. ;
Webb, B. ;
Sprogis, E. ;
Kang, S. K. ;
Polastre, R. ;
Horton, R. ;
Knickerbocker, J. U. .
57TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, 2007 PROCEEDINGS, 2007, :627-+
[10]   Current status of research and development for three-dimensional chip stack technology [J].
Takahashi, K ;
Terao, H ;
Tomita, Y ;
Yamaji, Y ;
Hoshino, M ;
Sato, T ;
Morifuji, T ;
Sunohara, M ;
Bonkohara, M .
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, 2001, 40 (4B) :3032-3037