Design and processing of integrated micro accelerometers using standard CMOS process

A capacitive accelerometer integrated with a switched-capacitor circuitry on the same chip has been implemented by using a 0.8 mu m DPDM (Double Polysilicon Double Metal) CMOS process. We will explain the working principle of the capacitive accelerometer, and describe the design and the post-processing of the capacitive CMOS accelerometer chip. Metal 1 layer is selected as the sacrificial layer. The sensing capacitor of the capacitive accelerometer is composed of poly 1 layer and metal 2 layer. The post-CMOS processing steps need one mask only, and phosphoric acid is used to etch the sacrificial layer for releasing the suspended structure. A switched-capacitor circuitry is for the use of detecting the output signal of the accelerometer The performance of this CMOS accelerometer demonstrates a bandwidth of 150Hz and an working range of +/-15g with a sensitivity of 120 mu V/g.