SOFF: An OpenCL High-Level Synthesis Framework for FPGAs

被引:13
|
作者
Jo, Gangwon [1 ]
Kim, Heehoon [2 ]
Lee, Jeesoo [2 ]
Lee, Jaejin [2 ]
机构
[1] ManyCoreSoft, Seoul 08826, South Korea
[2] Seoul Natl Univ, Dept Comp Sci & Engn, Seoul 08826, South Korea
来源
2020 ACM/IEEE 47TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE (ISCA 2020) | 2020年
基金
新加坡国家研究基金会;
关键词
Accelerator architectures; FPGAs; high level synthesis; parallel programming; pipeline processing;
D O I
10.1109/ISCA45697.2020.00034
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Recently, OpenCL has been emerging as a programming model for energy-efficient FPGA accelerators. However, the state-of-the-art OpenCL frameworks for FPGAs suffer from poor performance and usability. This paper proposes a high-level synthesis framework of OpenCL for FPGAs, called SOFF. It automatically synthesizes a datapath to execute many OpenCL kernel threads in a pipelined manner. It also synthesizes an efficient memory subsystem for the datapath based on the characteristics of OpenCL kernels. Unlike previous high-level synthesis techniques, we propose a formal way to handle variable-latency instructions, complex control flows, OpenCL barriers, and atomic operations that appear in real-world OpenCL kernels. SOFF is the first OpenCL framework that correctly compiles and executes all applications in the SPEC ACCEL benchmark suite except three applications that require more FPGA resources than are available. In addition, SOFF achieves the speedup of 1.33 over Intel FPGA SDK for OpenCL without any explicit user annotation or source code modification.
引用
收藏
页码:295 / 308
页数:14
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