SJ-LDMOS with high breakdown voltage and ultra-low on-resistance

被引：16
|
作者：
Chen, W. [1 ]
Zhang, B. [1 ]
Li, Z. [1 ]
机构：
[1] Univ Elect Sci & Technol China, Ctr IC Design, Chengdu 610054, Sichuan, Peoples R China
来源：
ELECTRONICS LETTERS | 2006年 / 42卷 / 22期
关键词：
D O I：
10.1049/el:20062751
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A new design concept is proposed to eliminate the substrate-assisted depiction effect in a super-junction (SJ) LDMOS. The key feature of the concept is that a non-uniform N-buried layer is implemented which compensates for the charge interaction between the P-substrate and SJ region, realising high breakdown voltage (> 700 V) and ultra-low on-resistance. Furthermore, the proposed device is compatible with smart power technology.
引用
收藏
页码：1314 / 1316
页数：3
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