Encrypted Physical Layer Communications Using Synchronized Hyperchaotic Maps

被引:10
作者
Tang, Xinyao [1 ]
Mandal, Soumyajit [2 ]
机构
[1] Case Western Reserve Univ, Dept Elect Comp & Syst Engn ECSE, Cleveland, OH 44106 USA
[2] Univ Florida, Dept Elect & Comp Engn ECE, Gainesville, FL 32611 USA
来源
IEEE ACCESS | 2021年 / 9卷
关键词
Encryption; Chaotic communication; Synchronization; Cryptography; Physical layer; System-on-chip; Wireless communication; Image encryption; 3D-bit scrambling; hyperchaos; synchronization; digital communications; matched filtering; CMOS;
D O I
10.1109/ACCESS.2021.3051810
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
With the proliferation of Internet-of-Things (IoT) devices at public facilities, work places, homes, and beyond, securing data communications is becoming increasingly challenging. This paper describes the analysis and practical implementation of synchronized hyperchaotic maps for securing short-range data links in IoT devices. The data is stream-encrypted in the physical layer using chaotic masking and decrypted using a synchronized chaotic map. Two different energy-efficient chaotic encryption schemes are proposed: 1) direct sampling and masking of analog sensor outputs, thus avoiding the need for analog-to-digital (ADC) conversion; and 2) bit scrambling and masking of digital data. Both schemes were initially investigated and simulated in MATLAB. The effective number of encryption keys when using such hyperchaotic maps was also studied. Simulation results were validated by implementing two maps on circuit boards using high-speed discrete components. Experimental results for digital communication show a bit error rate (BER) of approximate to 2 x 10(-6) at a bit rate of 10 kbps and a clock frequency of 0.5 MHz, making the approach feasible for high-fidelity real-time speech and image transmission without additional error control coding. An energy-efficient on-chip chaotic encryption system was developed using analog current-mode circuits and has a simulated power consumption of <100 mu W in the TSMC 180 nm CMOS process, which is sufficiently low for use in many battery-less miniaturized IoT sensor nodes.
引用
收藏
页码:13286 / 13303
页数:18
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