A wide range ultra-low power Phase-Locked Loop with automatic frequency setting in 130 nm CMOS technology for data serialisation

被引：1

作者：

Firlej, M. ^{[1
]}

Fiutowski, T. ^{[1
]}

Idzik, M. ^{[1
]}

Moron, J. ^{[1
]}

Swientek, K. ^{[1
]}

机构：

[1] AGH Univ Sci & Technol, Al Mickiewicza 30, PL-30059 Krakow, Poland

来源：

JOURNAL OF INSTRUMENTATION | 2015年 / 10卷

关键词：

VLSI circuits; Electronic detector readout concepts (gas; liquid); Electronic detector readout concepts (solid-state); Digital electronic circuits; PLL;

D O I：

10.1088/1748-0221/10/12/P12015

中图分类号：

TH7 [仪器、仪表];

学科分类号：

0804 ; 080401 ; 081102 ;

摘要：

The design and measurements results of a wide frequency range ultra-low power Phase-Locked Loop (PLL) for applications in readout systems of particle physics detectors are presented. The PLL was fabricated in a 130 nm CMOS technology. To allow the implementation of different data serialisation schemes multiple division factors (6, 8, 10, 16) were implemented in the PLL feedback loop. The main PLL block-VCO works in 16 frequency ranges/modes, switched either manually or automatically. A dedicated automatic frequency mode switching circuit was developed to allow simple frequency tuning. Although the PLL was designed and simulated for a frequency range of 30 MHz-3 GHz, due to the SLVS interface limits, the measurements were done only up to 1.3 GHz. The full PLL functionality was experimentally verified, confirming a very low and frequency scalable power consumption (0.7 mW at 1 GHz).

引用

页数：15