8.9-Megapixel Video Image Sensor With 14-b Column-Parallel SA-ADC

被引：68

作者：

Matsuo, Shinichiro ^{[1
]}

Bales, Timothy J.

Shoda, Masahiro ^{[1
]}

Osawa, Shinji ^{[1
]}

Kawamura, Katsuyuki ^{[1
]}

Andersson, Anders ^{[1
]}

Haque, Munirul ^{[1
]}

Honda, Hidenari ^{[1
]}

Almond, Bryan

Mo, Yaowu ^{[2
]}

Gleason, Jeffrey ^{[2
]}

Chow, Tony ^{[2
]}

Takayanagi, Isao ^{[1
]}

机构：

[1] Aptina Japan LLC, Tokyo 1080023, Japan

[2] Aptina LLC, San Jose, CA 95134 USA

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2009年 / 56卷 / 11期

关键词：

CMOS image sensors; column-parallel processing; digital column processor; high resolution; high sensitivity; low readout noise; low structural noise; successive approximation analog-to-digital converter (SA-ADC); HIGH-SPEED; CMOS; CAMERA;

D O I：

10.1109/TED.2009.2030649

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An 8.9-megapixel 60-frames/s video image sensor with a 14-b column-parallel analog-to-digital converter (ADC) has been developed. A gain amplifier, a 14-b successive approximation ADC (SA-ADC), and a new column digital processor are employed in each column. The SA-ADC has sufficient operation speed to convert the pixel reset and the pixel signal into digital data in a row operation cycle. The column digital processor receives bit serial data from the SA-ADC output and performs subtraction of the reset data from the signal data in order to reduce column fixed pattern noise (FPN). Column FPN is successfully reduced to 0.36 e(rms)(-) by this digital-domain column FPN correction. Low-voltage low-power serial video interface and noise decoupling on pixel drive voltages contribute to row-temporal-noise reduction to 0.31 e (-)(rms). Both column FPN and row temporal noise are not visible in spite of a low readout noise floor of 2.8 e(rms)(-).

引用

页码：2380 / 2389

页数：10

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