Analysis and optimization of the two-stage pipelined SAR ADCs

被引：3

作者：

Shen, Yi ^{[1
]}

Zhu, Zhangming ^{[1
]}

机构：

[1] Xidian Univ, Sch Microelect, 2 Taibai Rd, Xian 710071, Peoples R China

来源：

MICROELECTRONICS JOURNAL | 2016年 / 47卷

基金：

中国国家自然科学基金;

关键词：

Pipelined SAR ADC; MDAC; Linearity; High speed; Optimization; 10-BIT; POWER;

D O I：

10.1016/j.mejo.2015.10.018

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The two-stage pipelined SAR ADC (Successive Approximation Register Analog-to-Digital Convertor) is analyzed which consists of a SAR-based MDAC and a SAR ADC, with 1 bit redundancy to relax the requirement for the sub-ADC decision in accuracy. The stage resolution determines the performance of the ADC, which is optimized for high performance in linearity, noise, power, and speed. For the resolution of 10-bit, the optimal per stage resolution is about 5-bit in the first stage and 6-bit in the second stage. According to the analysis, a 10-bit two-stage pipelined SAR ADC was designed and fabricated in 180 nm CMOS, which achieves 56.04 dB SNDR and 5 mW power consumption from 1.8 V power supply at 50 MS/s. (C) 2015 Elsevier Ltd. All rights reserved.

引用

页码：40 / 44

页数：5

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