System-level modeling of a network switch SoC

被引：0

作者：

Paul, JM ^{[1
]}

Andrews, CP ^{[1
]}

Cassidy, AS ^{[1
]}

Thomas, DE ^{[1
]}

机构：

[1] Carnegie Mellon Univ, Elect & Comp Engn Dept, Pittsburgh, PA 15213 USA

来源：

ISSS'02: 15TH INTERNATIONAL SYMPOSIUM ON SYSTEM SYNTHESIS | 2002年

关键词：

computer-aided design; network switch; performance modeling; system modeling; memory visualization level design;

D O I：

10.1109/ISSS.2002.1227153

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We present the modeling of the high-level design of a next generation network switch from the perspective of a Computer Aided Design (CAD) team within the larger context of a design team consisting of an experienced network switch designer and an experienced VLSI hardware designer. After facilitating the design process, the CAD team observed how designers approach high-level designs, beyond RTL. We motivate the need for CAD support that allows designers to effectively manipulate what we refer to as Memory Visualization Level (MVL) design.

引用

页码：62 / 67

页数：6

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