The Deferred Event Model for Hardware-Oriented Spiking Neural Networks

被引:0
作者
Rast, Alexander [1 ]
Jin, Xin [1 ]
Khan, Mukaram [1 ]
Furber, Steve [1 ]
机构
[1] Univ Manchester, Sch Comp Sci, Manchester M13 9PL, Lancs, England
来源
ADVANCES IN NEURO-INFORMATION PROCESSING, PT II | 2009年 / 5507卷
基金
英国工程与自然科学研究理事会;
关键词
NEURONS;
D O I
暂无
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
Real-time modelling of large neural systems places critical demands on the processing system's dynamic model. With spiking neural networks it is convenient to abstract each spike to a point event. In addition to the representational simplification, the event model confers the ability to defer state updates, if the model does not propagate the effects of the current event instantaneously. Using the SpiNNaker dedicated neural chip multiprocessor as an example system, we develop models for neural dynamics and synaptic learning that delay actual updates until the next input event while performing processing in background between events, using the difference between "electronic time" and "neural time" to achieve real-time performance. The model relaxes both local memory and update scheduling requirements to levels realistic for the hardware. The delayed-event model represents a useful way to recast the real-time updating problem into a question of time to the next event.
引用
收藏
页码:1057 / 1064
页数:8
相关论文
共 17 条
[1]  
DAUD T, 1995, P SOC PHOTO-OPT INS, V2424, P489, DOI 10.1117/12.205250
[2]  
Dayan P., 2001, Theoretical neuroscience: Computational and mathematical modeling of neural systems
[3]   Neural systems engineering [J].
Furber, Steve ;
Temple, Steve .
JOURNAL OF THE ROYAL SOCIETY INTERFACE, 2007, 4 (13) :193-206
[4]   A neuronal learning rule for sub-millisecond temporal coding [J].
Gerstner, W ;
Kempter, R ;
vanHemmen, JL ;
Wagner, H .
NATURE, 1996, 383 (6595) :76-78
[5]  
GOLDBERG D, 2001, P 2001 IEEE INT S CI, P241
[6]   A VLSI array of low-power spiking neurons and bistable synapses with spike-timing dependent plasticity [J].
Indiveri, G ;
Chicca, E ;
Douglas, R .
IEEE TRANSACTIONS ON NEURAL NETWORKS, 2006, 17 (01) :211-221
[7]   Simple model of spiking neurons [J].
Izhikevich, EM .
IEEE TRANSACTIONS ON NEURAL NETWORKS, 2003, 14 (06) :1569-1572
[8]   Efficient Modelling of Spiking Neural networks on a Scalable Chip Multiprocessor [J].
Jin, Xin ;
Furber, Steve B. ;
Woods, John V. .
2008 IEEE INTERNATIONAL JOINT CONFERENCE ON NEURAL NETWORKS, VOLS 1-8, 2008, :2812-2819
[9]   SpiNNaker: Mapping Neural Networks onto a Massively-Parallel Chip Multiprocessor [J].
Khan, M. M. ;
Lester, D. R. ;
Plana, L. A. ;
Rast, A. ;
Jin, X. ;
Painkras, E. ;
Furber, S. B. .
2008 IEEE INTERNATIONAL JOINT CONFERENCE ON NEURAL NETWORKS, VOLS 1-8, 2008, :2849-2856
[10]   SILICON AUDITORY PROCESSORS AS COMPUTER PERIPHERALS [J].
LAZZARO, J ;
WAWRZYNEK, J ;
MAHOWALD, M ;
SIVILOTTI, M ;
GILLESPIE, D .
IEEE TRANSACTIONS ON NEURAL NETWORKS, 1993, 4 (03) :523-528