An ESD test reduction method for complex devices

被引：0

作者：

Maksimovic, Dejan ^{[1
]}

Blanc, Fabrice ^{[2
]}

Notermans, Guido ^{[1
]}

Smedes, Theo ^{[3
]}

Keller, Thomas ^{[1
]}

机构：

[1] ST Ericsson, CH-8045 Zurich, Switzerland

[2] Miniparc Polytec, ARM Grenoble Design Ctr, F-38000 Grenoble, France

[3] NXP Semicond, NL-6534 AE Nijmegen, Netherlands

来源：

MICROELECTRONICS RELIABILITY | 2009年 / 49卷 / 12期

关键词：

D O I：

10.1016/j.microrel.2009.10.010

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We define rules to reduce the ESD test complexity for chips with large pin count. These rules exploit the structural similarity in the pad-ring and have a long history of use without bad experiences. Using these rules an automated software tool can be developed for reduced ESD test generation. (C) 2009 Elsevier Ltd. All rights reserved.

引用

页码：1465 / 1469

页数：5