Geometrical optimization of multilevel interconnects using Cu and low-k dielectrics

A comparison of propagation time and cross-talk for different technology variations was carried out. The calculation of parasitics was based on electrostatic field simulation in two dimensions, which also allows bounds to be obtained for three-dimensional effects such as line crossings in upper levels. The dependence of IC performance on the materials used for metallization was modelled. The simulation results recommend the use of copper and low-k dielectrics as a desirable alternative for aluminum and SiO2. In addition to material substitutions, the circuit performance can be improved further by the optimization of the geometrical interconnection parameters such as the interconnect aspect ratio and the interlevel distance for the most critical interconnects. This is demonstrated for an advanced metallization scheme produced by a gap-fill process using encapsulated copper and low-k dielectrics.