Investigation of fundamental technology for 3D assembly

Three-dimensional assemblies are not only a semiconductor packaging technique but required several technologies of various fields such as the wafer process, the substrate process and the formed passive component technology. We studied a following four key technique for Three-dimensional assembly a core technology, the wafer thinner technique with stress relief process, the Ultra sonic bonding technique for low stress interconnection, through hole formed on Silicon had been investigated. In additionally, the embedded components technique has been studied. As an example of product, we made 50um thick Si chip was embedded in the organic substrate. In this paper, we introduce fundamental technique for theses.