Software Fault Insertion Testing for SIL Certification of Safety PLC-Based System

被引：0

作者：

Odarushchenko, Oleg ^{[1
]}

Striuk, Oleksiy ^{[1
]}

Leontiiev, Kostiantyn ^{[2
]}

Odarushchenko, Elena ^{[3
]}

机构：

[1] Radics LLC, Kropyvnytskiy, Ukraine

[2] RPC Radiy, Kropyvnytskiy, Ukraine

[3] Poltava State Agr Acad, Informat Syst & Technol Dept, Poltava, Ukraine

来源：

2020 IEEE 11TH INTERNATIONAL CONFERENCE ON DEPENDABLE SYSTEMS, SERVICES AND TECHNOLOGIES (DESSERT): IOT, BIG DATA AND AI FOR A SAFE & SECURE WORLD AND INDUSTRY 4.0 | 2020年

关键词：

I&C systems; PLC - programmable logic controller; fault insertion testing (FIT); software FIT; FIT procedures; FIT tools;

D O I：

10.1109/dessert50317.2020.9125006

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The problems of the safety PLC market are analyzed. A tendency of the PLCs transition for industrial applications (for example NPP I&C) in new technologies has been identified. The advantages of FPGA technology for developing safety-based PLCs in comparison with microprocessor technology are formulated. The fault insertion testing (FIT) is considered as one of the mandatory techniques applied in the process of the certification against requirements of IEC 61508 according to safety integrity level (SIL). The concept of the HW FIT-ability is generalized for SW components of FPGA PLC-based safety-critical I&C systems (FPICS) (SW FIT-ability). Procedures, techniques and tools taking into account existing set of insertion variants for SW faults are proposed.

引用

页码：80 / 84

页数：5

共 9 条

[1]

[Anonymous], 2011, TR1022983 EPRI

[2]

[Anonymous], 2009, TR1019181 EPRI

[3]

Babeshko E, 2015, 2015 INTERNATIONAL CONFERENCE ON INFORMATION AND DIGITAL TECHNOLOGIES (IDT), P22, DOI 10.1109/DT.2015.7222945

[4]

Goble W., 2015, EXIDA BLOG

[5] Fault injection techniques and tools [J].

Hsueh, MC ;

Tsai, TK ;

Iyer, RK .

COMPUTER, 1997, 30 (04) :75-+

[6]

IEC, 2010, IEC61508

[7]

Kharchenko V, 2014, PROCEEDINGS OF THE 22ND INTERNATIONAL CONFERENCE ON NUCLEAR ENGINEERING - 2014, VOL 6

[8] Fault injection in VHDL descriptions and emulation [J].

Leveugle, R .

IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS, 2000, :414-419

[9]

Odarushchenko O., P E W DES TEST S EWD, P188

← 1 →