A design of a 5.6 GHz frequency synthesizer with switched bias LIT VCO and low noise on-chip LDO regulator for 5G applications

被引：5

作者：

Kim, SungJin ^{[1
]}

Cheon, Ji-Hyeon ^{[1
]}

Lee, DongSoo ^{[1
]}

Pu, YoungGun ^{[1
]}

Yoo, Sang-Sun ^{[2
]}

Lee, Minjae ^{[3
]}

Hwang, Keum Cheol ^{[1
]}

Yang, Youngoo ^{[1
]}

Lee, Kang-Yoon ^{[1
]}

机构：

[1] Sungkyunkwan Univ, Coll Informat & Commun Engn, Suwon, South Korea

[2] Pyeongtaek Univ, Dept Smart Automobile, Pyeongtaek, South Korea

[3] Gwangju Inst Sci & Technol, Sch Informat & Commun, Gwangju, South Korea

来源：

INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS | 2019年 / 47卷 / 11期

基金：

新加坡国家研究基金会;

关键词：

delta-sigma modulator; frequency synthesizer; linear transconductance; low-noise LDO; switched bias;

D O I：

10.1002/cta.2687

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：1856 / 1868

页数：13

共 16 条

[1] A Dynamic Phase Error Compensation Technique for Fast-Locking Phase-Locked Loops [J].

Chiu, Wei-Hao ;

Huang, Yu-Hsiang ;

Lin, Tsung-Hsien .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2010, 45 (06) :1137-1149

[2] A 5.5-GHz 16-mW fast-locking frequency synthesizer in 0.18-μm CMOS [J].

Chiu, Wei-Hao ;

Chan, Tai-Shun ;

Lin, Tsung-Hsien .

2007 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE, PROCEEDINGS OF TECHNICAL PAPERS, 2007, :456-459

[3] A 28-GHz Quadrature Fractional-N Frequency Synthesizer for 5G Transceivers With Less Than 100-fs Jitter Based on Cascaded PLL Architecture [J].

El-Halwagy, Waleed ;

Nag, Amlan ;

Hisayasu, Philip ;

Aryanfar, Farshid ;

Mousavi, Pedram ;

Hossain, Masum .

IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, 2017, 65 (02) :396-413

[4]

Fanori L, 2014, PROC EUR SOLID-STATE, P335, DOI 10.1109/ESSCIRC.2014.6942090

[5]

Hung CM, 2002, IEEE J SOLID-ST CIRC, V37, P521

[6]

Ikeda S, 2012, IEEE ASIAN SOLID STA, P357

[7]

KELIU S, 2005, CMOS PLL SYNTHESIZER

[8] Reducing MOSFET 1/f noise and power consumption by switched biasing [J].

Klumperink, EAM ;

Gierkink, SLJ ;

van der Wel, AP ;

Nauta, B .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2000, 35 (07) :994-1001

[9] A low phase noise 30-GHz frequency synthesizer with linear transconductance VCO and dual-injection-locked frequency divider [J].

Lee, Dong-Soo ;

Cho, SungHun ;

Kim, SangYun ;

Lee, JaeYong ;

Hwang, KeumCheol ;

Yang, Youngoo ;

Seo, Mun-Kyo ;

Pu, YoungGun ;

Lee, Kang-Yoon .

ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2016, 86 (03) :365-376

[10] A Wide-Locking-Range Dual Injection-Locked Frequency Divider With an Automatic Frequency Calibration Loop in 65-nm CMOS [J].

Lee, Dong-Soo ;

Jang, Jae-Hyung ;

Park, Hyung-Gu ;

Pu, YoungGun ;

Hwang, Keum Cheol ;

Yang, Youngoo ;

Seo, Mun-Kyo ;

Lee, Kang-Yoon .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2015, 62 (04) :327-331

← 1 2 →