A novel hardware-efficient spatial orientation tree-based image compression algorithm and its field programmable gate array implementation

Set partitioning in hierarchical trees (SPIHT) has become a popular research topic for more than a decade now. This is because it is simple, besides having compression efficiency close to the state-of-the-art JPEG2000 standard. The main drawback of SPIHT is that it uses three lists to store addresses of coefficients during its operation. These lists are dynamic and in worst cases need to store more number of addresses than total coefficients. In this work, a novel hardware-efficient spatial orientation tree-based algorithm is proposed and its hardware implementation is carried out. The wavelet transformed image is partitioned into 2 x 2 blocks. Each node of spatial orientation tree (SOT) represent a block of coefficients, rather than a single coefficient. Two small state-tables are used in this algorithm to store the status of each block. In addition to this, two extremely small lists are used to store the node addresses of a single SOT tree. To store the state-tables and lists for 512 x 512 image, only 0.88% of the memory needed by SPIHT is required for five levels of dyadic decomposition. The peak-signal-to-noise ratio (PSNR) gain of 0.1 dB to 0.3 dB at low bit rates (below 1 bpp) and 0.6 dB to 1.2 dB at high bit rates (above 1.75 bpp) in comparison to SPIHT is observed for test image Lena. A field programmable gate array (FPGA) implementation targeted for Xilinx Zynq Z-7020 is presented in the paper. The proposed architecture saves 90% of the FPGA area used by SPIHT. The hardware efficiency of the proposed architecture is better in comparison to different existing architectures.