Parallel Multipliers for Quantum-Dot Cellular Automata

被引：26

作者：

Kim, Seong-Wan ^{[1
]}

Swartzlander, Earl E., Jr. ^{[1
]}

机构：

[1] Univ Texas Austin, Dept Elect & Comp Engn, Austin, TX 78712 USA

来源：

2009 IEEE NANOTECHNOLOGY MATERIALS AND DEVICES CONFERENCE | 2009年

关键词：

D O I：

10.1109/NMDC.2009.5167566

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper explores the optimization of parallel multipliers for Quantum-Dot Cellular Automata. To reduce the complexity, multipliers are designed with quasi-modularity to accommodate large word sizes. The regular quasi-modular product method is used to make n x n multipliers using 4 (n/2 x n/2) modules. This may be continued with further decomposition to 16 (n/4 x n/4) modules, etc. The last two rows in Wallace or Dadda reduction trees are summed by an adder that is 3n/2 - 1 bits long to produce the final product. This design is constructed using coplanar layouts and compared with other QCA multipliers (bit-serial and array multipliers). The delay, area and complexity are compared for several different operand sizes using the QCADesigner simulator.

引用

页码：68 / 72

页数：5

共 15 条

[1] Serial parallel multiplier design in quantum-dot cellular automata [J].

Cho, Heumpil ;

Swartzlander, Earl E., Jr. .

18TH IEEE SYMPOSIUM ON COMPUTER ARITHMETIC, PROCEEDINGS, 2007, :7-+

[2]

Dadda Luigi, 1965, Alta frequenza, V34, P349

[3] Pipelined array multiplier based on quantum-dot cellular automata [J].

Hanninen, Ismo ;

Takala, Jarmo .

2007 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN, VOLS 1-3, 2007, :938-941

[4] Clocking of molecular quantum-dot cellular automata [J].

Hennessy, K ;

Lent, CS .

JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 2001, 19 (05) :1752-1755

[5] Design of sequential circuits by quantum-dot cellular automata [J].

Huang, J. ;

Momenzadeh, M. ;

Lombardi, F. .

MICROELECTRONICS JOURNAL, 2007, 38 (4-5) :525-537

[6] The robust QCA adder designs using composable QCA building blocks [J].

Kim, Kyosun ;

Wu, Kaijie ;

Karri, Ramesh .

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2007, 26 (01) :176-183

[7] Bennett clocking of quantum-dot cellular automata and the limits to binary logic scaling [J].

Lent, Craig S. ;

Liu, Mo ;

Lu, Yuhui .

NANOTECHNOLOGY, 2006, 17 (16) :4240-4251

[8] Device architecture for computing with quantum dots [J].

Lent, CS ;

Tougaw, PD .

PROCEEDINGS OF THE IEEE, 1997, 85 (04) :541-557

[9]

Niemier MT, 2001, CONF PROC INT SYMP C, P166, DOI 10.1109/ISCA.2001.937445

[10] Quantum-dot cellular automata: Line and majority logic gate [J].

Snider, GL ;

Orlov, AO ;

Amlani, I ;

Bernstein, GH ;

Lent, CS ;

Merz, JL ;

Porod, W .

JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, 1999, 38 (12B) :7227-7229

← 1 2 →