Ultra High Density SoIC with Sub-micron Bond Pitch

被引：35

作者：

Chen, Y. H. ^{[1
]}

Yang, C. A. ^{[1
]}

Kuo, C. C. ^{[1
]}

Chen, M. F. ^{[1
]}

Tung, C. H. ^{[1
]}

Chiou, W. C. ^{[1
]}

Yu, Douglas ^{[1
]}

机构：

[1] Taiwan Semicond Mfg Co Ltd, Integrated Interconnect & Packaging, R&D, 166,Pk Ave 2,Hsinchu Sci Pk, Hsinchu 30075, Taiwan

来源：

2020 IEEE 70TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2020) | 2020年

关键词：

3DIC; SoIC; WLSI; ultra high bond density; sub-micron bond pitch; chiplets integration; system scaling; system deep partition;

D O I：

10.1109/ECTC32862.2020.00096

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An ultrahigh density 3D technology, SoIC_UHD, with sub-micron pitch inter-chip vertical interconnect enabling a density >= 1.2 million bonds/mm(2) is reported for the first time. Proven yield and reliability of SoIC_UHD are demonstrated with a foundry front-end wafer level 3D heterogeneous system integration (WLSI) platform. SoC deep partitioning into mini chiplets with SoIC_UHD can extend Moore's Law for longer term than that achieved by conventional 3DIC stacking with micro-bumps. Micro-system scaling, which is complementary to transistor scaling, can continue to improve transistor density, system PPA, and cost competitiveness.

引用

页码：576 / 581

页数：6